As is known in the art, FETs are used in MMICs in a wide variety of applications. One FET configuration is shown in FIG. 1 to include a gate electrode disposed on an upper surface of a single crystal substrate structure. The gate electrode has a plurality of fingers; pairs thereof being disposed on each side of a corresponding one of a plurality of fingers of a drain electrode also disposed on the upper surface of the structure. The source electrode includes a plurality of source pads disposed on the upper surface of the structure between other pairs of the gate fingers as shown in FIG. 1. The source pads are connected through vias passing through the structure to a common source electrode, or ground plane, not shown, disposed on the lower, or bottom, surface of the structure.
At lower frequencies, the topology described above and shown in FIG. 1, is also used with the multiple-source pads, interconnected by an air-bridge conductors, not shown, disposed over the upper surface of the structure and grounded to a ground plane on the lower surface of the structure with vias at the two end source pads.
As is also known in the art, one application for a FET is in an oscillator circuit. A commonly used oscillator circuit uses a grounded gate electrode. Thus, it is difficult to use the FET structure described above in connection with FIG. 1 in a common-gate (i.e., grounded gate) configuration because devices using the structure in FIG. 1 are very unstable unless parasitic inductances and capacitances in the gate circuits are minimized. In the device of FIG. 1, the individual gate fingers are connected to a common gate “bar” or pad, as shown, and this distribution of gate fingers, along with the bar, creates significant parasitic inductances and capacitances particularly at millimeter (mm) wavelength operation. Furthermore, it is ambiguous as to how to model exactly where the gate feed point is from an external (to the device) perspective for circuit design. These ambiguities, along with the unwanted gate parasitics, tend to make common-gate structures very difficult at high frequencies, and often result in multiple design iterations in order to achieve success.